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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com | copyright ? intersil corporation 1999 hs-2420rh radiation hardened fast sample and hold description the hs-2420rh is a radiation hardened monolithic circuit consisting of a high performance operational ampli?er with its output in series with an ultra-low leakage analog switch and mosfet input unity gain ampli?er. with an external hold capacitor connected to the switch output, a versatile, high performance sample-and-hold or track-and- hold circuit is formed. when the switch is closed, the device behaves as an operation ampli?er, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. when the switch is opened the output will remain at its last level. performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. accuracy to better than 0.01% is achievable over the temperature range. fast acquisition is coupled with superior droop characteristics, even at high temperatures. high slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. the ability to operate at gains greater than 1 frequently eliminates the need for external scaling ampli?ers. the device may also be used as a versatile operational ampli?er with a gated output for applications such as analog switches, peak holding circuits, etc. features ? maximum acquisition time - 10v step to 0.1%. . . . . . . . . . . . . . . . . . . . . . . . . . . 4 m s - 10v step to 0.01%. . . . . . . . . . . . . . . . . . . . . . . . . . 6 m s ? maximum drift current . . . . . . . . . . . . . . . . . . . . . .10na (maximum over temperature) ? ttl compatible control input ? power supply rejection . . . . . . . . . . . . . . . . . . . . . .3 80db ? total gamma dose. . . . . . . . . . . . . . . . . 1 x 10 5 rad(si) ? no latch-up applications ? data acquisition systems ? d to a deglitcher ? auto zero systems ? peak detector ? gated op amp ordering information part number temperature range package HS1-2420RH-Q -55 o c to +125 o c 14 lead cerdip july 1995 14 lead ceramic dual-in-line frit seal package (cerdip) mil-std-1835, gdip1-t14 top view in- in+ offset adjust offset adjust v- nc output sample/hold gnd nc hold capacitor nc v+ nc control 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 pin dip functional diagram note: pin numbers correspond to dip package only. - + offset adjust v+ 34 5 - + 7 output 11 hold capacitor - input + input sample/ hold control v- gnd 5 13 14 2 1 hs-2420rh spec number 518855 file number 3554.1 pinout
2 speci?cations hs-2420rh absolute maximum ratings reliability information voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . +40v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24v digital input voltage ( s/h pin) . . . . . . . . . . . . . . . . . . . . . .+8v, -15v output current . . . . . . . . . . . . . . . . . . . . . . . short circuit protected storage temperature range . . . . . . . . . . . . . .-65 o c < t a < +150 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +275 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c thermal resistance q ja q jc cerdip package . . . . . . . . . . . . . . . . . . . 74 o c/w 18 o c/w maximum power dissipation at +125 o c cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68w if device power exceeds package dissipation capability, derate linearly at the following rate cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mw/ o c esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000v caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. recommended operating conditions operating temperature range . . . . . . . . . . . . .-55 o c < t a < +125 o c operating supply voltage ( vsupply) . . . . . . . . . . . . . . . . . . . 15v analog input voltage (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10v logic level low (vil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 0.8v logic level high (vih) . . . . . . . . . . . . . . . . . . . . . . . . . 2.0v to 5.0v table 1. dc electrical performance characteristics device tested at v+ = +15v, v- = -15v, vil = 0.8v (sample); vih = 2.0v (hold); ch = 1000pf, -input tied to output, unless other wise speci?ed parameter symbol conditions group a subgroups temperature limits units min max input offset voltage vio 1 +25 o c-44mv 2, 3 -55 o c, +125 o c-6 6 mv input bias current ib+ 1 +25 o c -200 200 na 2, 3 -55 o c, +125 o c -400 400 na ib- 1 +25 o c -200 200 na 2, 3 -55 o c, +125 o c -400 400 na input offset current iio 1 +25 o c -50 50 na 2, 3 -55 o c, +125 o c -100 100 na open loop voltage gain +avs rl = 2k w , cl = 50pf, vout = +10v 1 +25 o c 25 - kv/v 2, 3 -55 o c, +125 o c 25 - kv/v -avs rl = 2k w , cl = 50pf, vout = -10v 1 +25 o c 25 - kv/v 2, 3 -55 o c, +125 o c 25 - kv/v common mode rejection ratio -cmrr v+ = 25v, v- = -5v, vout = +10v, vs/h = 10.8v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db +cmrr v+ = 5v, v- = -25v, vout = -10v, vs/h = 9.2v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db output current +io vout = +10v 1 +25 o c +15.0 - ma -io vout = -10v 1 +25 o c -15.0 - ma output voltage swing +vop rl = 2k w , cl = 50pf 1 +25 o c +10.0 - v 2, 3 -55 o c, +125 o c -10.0 - v -vop rl = 2k w , cl = 50pf 1 +25 o c - -10.0 v 2, 3 -55 o c, +125 o c - -10.0 v power supply current +icc 1 +25 o c - 5.5 ma -icc 1 +25 o c -3.5 - ma power supply rejection ratio +psrr v+ = 10v and 20v, v- = -15v and -15v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db -psrr v+ = 15v and 15v, v- = -10v and -20v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db spec number 518855
3 speci?cations hs-2420rh digital input current iin1 vin1 = 0v 1 +25 o c - 800 m a 2, 3 -55 o c, +125 o c - 800 m a iin2 vin2 = 5.0v 1 +25 o c-20 m a 2, 3 -55 o c, +125 o c- 20 m a digital input voltage vil 1 +25 o c - 0.8 v 2, 3 -55 o c, +125 o c - 0.8 v vih 1 +25 o c 2.0 - v 2, 3 -55 o c, +125 o c 2.0 - v drift current id vin = 0v, rl = 2k w , cl = 50pf, s/h = 4.0v 2 +125 o c -10 10 na table 2. ac electrical performance characteristics device tested at v+ = +15v, v- = -15v, vil = 0.8v (sample), vih = 2.0v (hold), ch = 1000pf, -input tied to output, unless other wise speci?ed parameter symbol conditions group a subgroup temperature limits units min max hold step error verror vs/h = 0v and 4v, trise (vs/h) ? 30ns (note 1) 9 +25 o c -20 20 mv transient response rise time and fall time tr(tr) cl = 50pf, rl = 2k w , av = +1, vout = 200mvp-p 9 +25 o c - 100 ns tr(tf) 9 +25 o c - 100 ns transient response overshoot tr(+os) cl = 50pf, rl = 2k w , av = +1, vout = 200mvp-p 9 +25 o c - 40 % tr(-os) 9 +25 o c - 40 % transient response slew rate tr(+sr) cl = 50pf, rl = 2k w , av = +1, vout = 10vp-p 9 +25 o c 3.5 - v/ m s tr(-sr) 9 +25 o c 3.5 - v/ m s note: 1. verror = vout (vs/h = 0v) - vout (vs/h = 4v) table 3. electrical performance characteristics device tested at v+ = +15v, v- = -15v, vil = 0.8v (sample), vih = 2.0v (hold), ch = 1000pf, -input tied to output, unless other wise speci?ed parameter symbol conditions note temperature limits units min max hold mode feedthrough attenuation vatten rl = 2k w , cl = 50pf, av = +1, vin = 20vp-p, fin = 50khz 1 +25 o c, -55 o c, +125 o c 70 - db gain bandwidth product gbwp rl = 2k w , cl = 50pf, av = +1, vin = 100mvp-p 1 +25 o c 2.5 - mhz acquisition time (0.1%) +tacq (0.1%) rl = 2k w , cl = 50pf, av = +1, vout = 0v and +10v 1 +25 o c-4 m s -tacq (0.1%) rl = 2k w , cl = 50pf, av = +1, vout = 0v and -10v 1 +25 o c-4 m s acquisition time (0.01%) +tacq (0.01%) rl = 2k w , cl = 50pf, av = +1, vout = 0v and +10v 1 +25 o c-6 m s -tacq (0.01%) rl = 2k w , cl = 50pf, av = +1, vout = 0v and -10v 1 +25 o c-6 m s note: 1. parameters listed in table 3 are controlled via design or process parameters and are not directly tested at ?nal product ion. these parameters are characterized upon initial design release and upon design changes which would affect these characteristics. table 1. dc electrical performance characteristics (continued) device tested at v+ = +15v, v- = -15v, vil = 0.8v (sample); vih = 2.0v (hold); ch = 1000pf, -input tied to output, unless other wise speci?ed parameter symbol conditions group a subgroups temperature limits units min max spec number 518855
4 speci?cations hs-2420rh table 4. dc electrical performance characteristics post 100krad device tested at v+ = +15v, v- = -15v, vil = 0.8v (sample); vih = 2.0v (hold); ch = 1000pf, -input tied to output, unless other wise speci?ed parameter symbol conditions group a subgroups temperature limits units min max input offset voltage vio 1 +25 o c-66mv input bias current ib+ 1 +25 o c -400 400 na ib- 1 +25 o c -400 400 na input offset current iio 1 +25 o c -100 100 na open loop voltage gain +avs rl = 2k w , cl = 50pf, vout = +10v 1 +25 o c 25 - kv/v 2, 3 -55 o c, +125 o c 25 - kv/v -avs rl = 2k w , cl = 50pf, vout = -10v 1 +25 o c 25 - kv/v 2, 3 -55 o c, +125 o c 25 - kv/v common mode rejection ratio -cmrr v+ = 25v, v- = -5v, vout = +10v, vs/h = 10.8v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db +cmrr v+ = 5v, v- = -25v, vout = -10v, vs/h = 9.2v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db output current +io vout = +10v 1 +25 o c +12.0 - ma -io vout = -10v 1 +25 o c -12.0 - ma output voltage swing +vop rl = 2k w , cl = 50pf 1 +25 o c +10.0 - v 2, 3 -55 o c, +125 o c +10.0 - v -vop rl = 2k w , cl = 50pf 1 +25 o c - -10.0 v 2, 3 -55 o c, +125 o c - -10.0 v power supply current +icc 1 +25 o c - 5.5 ma -icc 1 +25 o c -3.5 - ma power supply rejection ratio +psrr v+ = 10v and 20v, v- = -15v and -15v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db -psrr v+ = 15v and 15v, v- = -10v and -20v 1 +25 o c80-db 2, 3 -55 o c, +125 o c80 - db digital input current iin1 vin1 = 0v 1 +25 o c - 800 m a 2, 3 -55 o c, +125 o c - 800 m a iin2 vin2 = 5.0v 1 +25 o c-20 m a 2, 3 -55 o c, +125 o c- 20 m a digital input voltage vil 1 +25 o c - 0.8 v 2, 3 -55 o c, +125 o c - 0.8 v vih 1 +25 o c 2.0 - v 2, 3 -55 o c, +125 o c 2.0 - v drift current id vin = 0v, rl = 2k w , cl = 50pf, s/h = 4.0v 2 +125 o c -10 10 na spec number 518855
5 speci?cations hs-2420rh table 4a. ac electrical performance characteristics post 100krad device tested at v+ = +15v, v- = -15v, vil = 0.8v (sample), vih = 2.0v (hold), ch = 1000pf, -input tied to output, unless other wise speci?ed parameter symbol conditions group a subgroup temperature limits units min max hold step error verror vs/h = 0v and 4v, trise (vs/h) ? 30ns (note 1) 9 +25 o c -20 20 mv transient response rise time and fall time tr(tr) cl = 50pf, rl = 2k w , av = +1, vout = 200mvp-p 9 +25 o c - 100 ns tr(tf) 9 +25 o c - 100 ns transient response overshoot tr(+os) cl = 50pf, rl = 2k w , av = +1, vout = 200mvp-p 9 +25 o c - 40 % tr(-os) 9 +25 o c - 40 % transient response slew rate tr(+sr) cl = 50pf, rl = 2k w , av = +1, vout = 10vp-p 9 +25 o c 2.0 - v/ m s tr(-sr) 9 +25 o c 2.0 - v/ m s note: 1. verror = vout (vs/h = 0v) - vout (vs/h = 4v) table 5. burn-in delta parameters (t a = +25 o c) parameters delta limits vio 2.0mv ibias 75na iio 75na table 6. applicable subgroups conformance group mil-std-883 method group a subgroups tested for -q recorded for -q initial test 100% 5004 1, 9 1 interim test 100% 5004 1, 9, d 1, d pda 100% 5004 1, d final test 100% 5004 2, 3, 10, 11 group a (note 1) sample 5005 1, 2, 3, 9, 10, 11 subgroup b5 sample 5005 1, 2, 3 1, 2, 3 subgroup b6 sample 5005 1 group d sample 5005 1 group e, subgroup 2 sample 5005 1 note: alternate group a testing may be exercised in accordance with method 5005 of mil-std-883. spec number 518855
6 test circuits figure 1. test fixture schematic (switch positions s1 - s8 determine configuration) note: compute hold mode feedthrough attenuation from the formula: where vout hold = peak-peak value of output sinewave during the hold mode. figure 2. hold mode feedthrough attenuation gbwp is the frequency of vinput at which: figure 3. gain bandwidth product dut - + a s/h -vcc +vcc ch = 1000pf 50 w 2 21 1 s2 s1 2 1 s6 1 2 s7 s7 1 2 50 w vac aout eout 50 w 1m w 4 3 2 1 s8 3 2 s3 1 +vcc gnd 50pf 2k w 1 s5 open 3 2 s4 1 100k w vdc 10k w iload null amp x1 x-1 buffer 100k w all resistors = 1% all capacitors = 10% + - + - ch = vout 50pf 2k w +15v -15v 1000pf dut vin out a0 en in2 in1 in3 in4 in5 in6 in7 in8 a2 a1 sinewave input sample/hold control input +5v + - feedthroughattenua tion 20 log vout hold vin hold ---------------------------------- - ? ?? = ch = vout 50pf 2k w +15v -15v 1000pf dut s/h 50 w + - 20 log vout vinput --------------------- - ? ?? 3db C = spec number 518855 hs-2420rh
7 figure 4. acquisition time (tacq to 0.01% is shown, tacq to 0.1% is done in the same manner) figure 5 test circuits (continued) increment t2 by 50ns (50ns longer delay) send sample command set t2 to 7 m s initially digitize v1 at t1 ( ? 10 m s) digitize v2 at t2 decrement t2 by 50ns calculate v1 - v2 is d v 3 0.01%? no yes course tacq measurement loop decrement t2 by 50ns digitize v1 at t1 ( ? 10 m s) digitize v2 at t2 calculate v1 - v2 is d v 3 0.01%? record tacq no yes fine tacq measurement loop note: see test diagram, timing diagram computer controller v1 digitizer v2 digitizer v1 v2 t2 variable delay t2 delay control t1 ? 10 m s 1000pf 2k w t1 - + - + s/h control hs-2420rh +10v 0v 0v -10v or 50pf delay spec number 518855 hs-2420rh
8 timing waveforms figure 6. timing diagram for acquisition time, (positive tacq case) figure 7a figure 7b figure 7. overshoot, rise and fall time waveforms figure 8a figure 8b figure 8. slew rate waveforms typical performance curves vsupply = 15vdc, t a = +25 o c, ch = 1000pf, unless otherwise speci?ed figure 9. typical sample and hold performance as a function of holding capacitor figure 10. broadband noise characteristics 10v 2v 0v 0v vin (pos tacq case) s/h control dut output (pos tacq case) 0v 10v t1 ? 10 m s (t1 digitizer command) (t2 digitizer command) t1 t2 t2 0.01% or 0.1% envelope +v 0v -v 0v input +os, tr -os, tf vpeak 90% 10% 90% 10% vpeak vfinal tr tf vfinal -v +v -v +v +sl -sl input +v +v 75% 25% 25% 75% -v -v d t d t 1000 100 10 1.0 0.1 0.01 10pf 100pf 1000pf 0.01mf 0.1mf 1.0mf drift during hold at +25 o c mv/s min sample time for 0.1% accuracy 10v swings (ms) unity gain phase margin (deg) hold step offset error (mv) slew rate/ charge rate v/(ms) unity gain bandwidth (mhz) ch value 1000 100 10 1 mv rms 10 100 1k 10k 100k 1m bandwidth lower 3db frequency = 10hz output noise hold mode equiv. input noise sample mode - 100k source resistance equiv. input noise sample mode - 0k source resistance spec number 518855 hs-2420rh
9 figure 11. drift current vs temperature figure 12. open loop frequency response figure 13. hold mode feedthrough attenuation ch = 1000pf figure 14. open loop phase response burn-in circuit hs-2420rh ceramic dip notes: r1 = 100k w 5% (per socket) c1 = c2 = 0.1 m f (one per row) or 0.01 m f (one per socket) d1 = d2 = 1n4002 or equivalent (per board) irradiation circuit notes: v1 = +15v v2 = -15v r = 100k w typical performance curves vsupply = 15vdc, t a = +25 o c, ch = 1000pf, unless otherwise speci?ed (continued) 1000 100 10 1 id (pa) -50 -25 0 +25 +50 +75 +100 +125 temperature ( o c) 100 80 60 40 20 0 -20 open loop voltage gain (db) 10 100 1k 10k 100k 1m 10m 100m frequency (hz) ch = 100pf ch = 1000pf ch = 1.0 m f ch = 0.1 m f ch = 0.01 m f -30 -40 -50 -60 -70 -80 -90 attenuation (db) 100 1k 10k 100k 1m 10m 10v sinusoidal input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 240 open loop phase angle (degrees) 10 100 1k 10k 100k 1m 10m 100m frequency (hz) ch = 1.0 m f ch = 0.1 m f ch =1000pf ch 100pf ch = 0.01 m f 1 2 3 4 5 6 7 14 13 12 11 10 9 8 c2 d2 d1 c1 -15v +15v r1 -in +in off adj -v nc out off adj s/h ctl gnd nc hold cap nc +v nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v1 r v2 gnd gnd spec number 518855 hs-2420rh
10 hs-2420rh offset and gain adjustment offset adjustment the offset voltage of the hs-2420rh may be adjusted using a 100k w trim pot, as shown in figure 15. the recommended adjustment procedure is: 1. apply zero volts to the sample-and-hold input, and a square wave to the s/h control. 2. adjust the trim pot for zero volts output in the hold mode. gain adjustment the linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (ch = 1000pf). in some applications (d/a deglitcher, a/d converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. the two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. the recommended procedure for adjusting gain error is: 1. perform offset adjustment. 2. apply the nominal input voltage that should produce a +10v output. 3. adjust the trim pot for +10v output in the hold mode. 4. apply the nominal input voltage that should produce a -10v output. 5. measure the output hold voltage (v-10 nominal). adjust the trim pot for an output hold voltage of v-10 nominal () 10v C () + 2 --------------------------------------------------------------------------- - spec number 518855 figure 14. hold step vs input voltage figure 15. basic sample-and-hold (top view) figure 16. inverting configuration figure 17. noninverting configuration +10 +5 -5 -10 -15 -20 -25 -30 -35 -10 -5 +5 +10 dc input voltage (v) hold step voltage (v) ch = 0.1 m f ch = 10,000pf ch = 1000pf ch = 100pf +in v- 100k w offset trim ( 25mv range) out -in v+ ch s/h control - +- + hs-2420rh -in +in out s/h control input ri output 0.002rf rf s/h control input hs-2420rh gain ~ -rf ri +in -in out s/h control input ri output 0.002ri rf s/h control input hs-2420rh gain ~ i + -rf ri
11 v+ ch out v- rp s/h ctl gnd r5 q5 q106 r3 q7 q3 q11 q8 q10 q13 r11 q12 q14 q16 q103 q17 q2 q4 q15 q6 q19 q18 q20 q21 q22 q26 q24 q25 q23 q28 q27 q31 q33 offset adjust r1 r2 q29 q30 q32 r13 q34 q38 q35 q39 q40 q41 q44 q43 q42 q100 q56 q101 q45 q48 q50 q46 q53 q55 q51 q52 q54 c2 r7 q57 q59 q58 q64 q65 q66 q72 q74 q73 c3 15pf q75 r8 r9 r10 c4 q60 c5 q77 q76 q69 q67 q68 q78 q70 q79 q63 q102 q62 q71 q81 r14 q80 in+ q9 q105 in- hs-2420rh schematic spec number 518855
12 intersil space level product flow -q wafer lot acceptance (all lots) method 5007 (includes sem) (note 1) gamma radiation veri?cation (each wafer) method 1019, 4 samples/wafer, 0 rejects 100% die attach 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a csi and/or gsi pre-cap (note 7) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind, method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in, condition a, 240 hours, +125 o c or equivalent, method 1015 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% pda, method 5004 (note 2) 100% final electrical test 100% fine/gross leak, method 1014 100% radiographic (x-ray), method 2012 (note 3) 100% external visual, method 2009 sample - group a, method 5005 (note 4) sample - group b, method 5005 (note 5) sample - group c, method 5005 (notes 5, 6) 100% data package generation (note 8) csi and/or gsi final (note 7) notes: 1. modi?ed sem inspection, not compliant to mil-std-883, method 2018. this device does not meet the class s minimum metal step coverage of 50%. the metal does meet the current density requirement of <2e 5 a/cm 2 . data provided upon request. 2. failures from subgroup 1 and deltas are used for calculating pda. the maximum allowable pda = 5%. 3. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 4. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 5. group b and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should i nclude separate line items for group b test, group b samples, group d test and group d samples. 6. group d generic data, as de?ned by mil-i-38535, is optional and will not be supplied unless required by the p.o. when require d, the p.o. should include a separate line item for group d generic data. generic data is not guaranteed to be available and is theref ore not available in all cases. 7. csi and/or gsi inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should include separate line items for csi pre-cap inspection, csi final inspection, gsi pre-cap inspection, and/or gsi final inspection. 8. data package contents: cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qua ntity). wafer lot acceptance report (method 5007). includes reproductions of sem photos with percent of step coverage. gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. x-ray report and ?lm. includes penetrometer measurements. screening, electrical, and group a attributes (screening attributes begin after package seal). lot serial number sheet (good units serial number and lot number). variables data (all delta operations). data is identi?ed by serial number. data header includes lot number and date of test. group b and d attributes and/or generic data is included when required by the p.o. the certi?cate of conformance is a part of the shipping invoice and is not part of the data book. the certi?cate of conformance is signed by an authorized quality representative. spec number 518855 hs-2420rh
13 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com hs-2420rh metallization topology die dimensions: 97 mils x 61 mils x 19 mils metallization: type: al thickness: 16k ? 2k ? glassivation: type: silox thickness: 14k ? 2k ? worst case current density: 2.0 x 10 5 a/cm 2 transistor count: 78 process: bipolar-di metallization mask layout hs-2420rh +in (2) off adj (3) off adj (4) v- (5) (7) out (9) v+ (11) hold cap (13) gnd -in (1) s/h control (14) spec number 518855

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